The present invention relates generally to the field of host processor to peripheral interfacing, and more particularly to a bus interface circuit for use in conjunction with a peripheral device having a clock that is not synchronized with the host processor clock.
Digital system applications that require a host processor to be interfaced with peripheral processing devices are prevalent. In such applications, the peripheral device is typically programmed to carry out input/output operations and/or data processing separately from the host processor. Consequently, such a peripheral device may contain its own processor, input/output circuitry, clock and control circuitry, and different addressable memory locations.
In such applications it is not always desirable to synchronize the peripheral clock with the clock in the host processor, so the peripheral clock can run at any speed relative to the host processor clock (either faster or slower). As a result of the difference between the peripheral and host microprocessor clocks, as well as the architecture and particular type of memory units employed in the peripheral device, the access time for different addressable memory locations within the peripheral can vary.
For a host processor to access (i.e., write data to and read data from) memory locations within the above described general peripheral processing device, an interfacing circuit is required for coupling the host processor and peripheral address and data buses, and to provide the appropriate timing for data transfers.
Consequently, there exists a need for a generic bus interface circuit for interfacing a host processor with a processing peripheral device, where the host processor and peripheral can have different asynchronous clocks, and peripheral memory locations accessible to the processor can have different access times.
As digital systems evolve to the point where the host processor, memory and several peripheral subsystems are all co-located on the same semiconductor substrate, it is important to minimize power dissipation and to conserve gate count within the interconnect structure. Furthermore, it is desirable to have circuit modules, (referred to as core circuits, or cells) that can be designed once and the designs reused and interconnected in a number of different digital systems in different combinations.
An illustrative embodiment of the present invention seeks to provide a bus for interconnecting common peripherals operating asynchronously to a host processor in a gate-efficient, low power implementation that can support zero wait state bus transactions and that avoids or minimizes above-mentioned problems.
Aspects of the invention are specified in the claims. In carrying out principles of the present invention a method for transferring a plurality of data on a data bus connected between a first device operating in accordance with a first clock signal and a second device operating in accordance with a second clock signal, comprises the steps of: initiating a transfer of a plurality of data in response to asserting a request signal by the second device; starting a first data transfer between the first device and the second device by the first device asserting a strobe signal on the data bus, the strobe signal having at least a first pulse, wherein the strobe signal is synchronized to the first clock signal; completing the first data transfer by the second device asserting a ready signal on the data bus synchronized with the strobe signal; and repeating the steps of starting a data transfer and completing a data transfer until the second device asserts an end signal to terminate the transfer of the plurality of data.
According to another feature of the invention, a digital system having data bus for transferring a plurality of data connected between a first device operating in accordance with a first clock signal and a second device operating in accordance with a second clock signal, comprises: control circuitry in the second device having a first output connected to the bus for initiating a transfer of a plurality of data in response to asserting a request signal and a second output connected to the bus for asserting an end signal to terminate the transfer of the plurality of data; strobe circuitry on the first device connected to the data bus and to the first clock signal, operable to start a first data transfer between the first device and the second device in response to the request signal by asserting a strobe signal on the data bus, the strobe signal having at least a first pulse, wherein the strobe signal is synchronized to the first clock signal; and ready circuitry on the second device connected to the data bus for completing the first data transfer by asserting a ready signal on the data bus synchronized with the strobe signal.
According to another feature of the invention, a FIFO type buffer is included on the second device connected to the data buss; and the control circuit on the second device is operable to assert the end signal in response to the FIFO type buffer becoming approximately full or approximately empty.
These and other features of the invention that will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.